一位元加法器系統時脈設計與測試

module top;
wire a, b, cin;
system_clock #400 clock1(cin);
system_clock #200 clock2(a);
system_clock #100 clock3(b);

and a1(out1,a,b);
xor a1(out2,a,b);
and a2(out3,out2,cin);
xor a2(sum,out2,cin);
or c(cout,out1,out3);

endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule