期末考試

module top;
wire a, b, c, d, f;
system_clock #400 clock1(a);
system_clock #200 clock2(b);
system_clock #100 clock3(c);
system_clock #50 clock4(d);

not a1(A,a);
not b1(B,b);
not c1(C,c);
not d1(D,d);
and f1(F1,a,C,D);
and f2(F2,a,b,C);
and f3(F3,a,b,d);
and f4(F4,b,C,d);
and f5(F5,A,B,c);
or out(F,F1,F2,F3,F4,F5);


endmodule`
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

期中

module top;
wire a, b, c, d, f;
system_clock #400 clock1(a);
system_clock #200 clock2(b);
system_clock #100 clock3(c);
system_clock #50 clock4(d);

not a1(A,a);
not b1(B,b);
not c1(C,c);
not d1(D,d);
and f1(F1,A,C,d);
and f2(F2,A,c,D);
and f3(F3,B,C,d);
and f4(F4,B,c,D);
or out(F,F1,F2,F3,F4);


endmodule`
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

二位元加法器結構模式

module top;

wire [1:0] A, B, Sum;
wire Cout, Cin;

system_clock #400 clock(Cin);
system_clock #200 clock(A[1]);
system_clock #100 clock(B[0]);
system_clock #200 clock(B[1]);
system_clock #100 clock(A[0]);


adder2 M2(Cout, Sum, A, B, Cin);

endmodule

module adder2(Cout, Sum, A, B, Cin);
output [1:0] Sum;
output Cout;
input [1:0] A, B;
input Cin;

adder1 lo (C0,Sum[0],A[0],B[0],Cin);
adder1 hi (Cout,Sum[1],A[1],B[1],C0);

endmodule

module adder1(Cout, Sum, A, B, Cin);
output Cout, Sum;
input A, B, Cin;
not I1(Anot,A);
not I2(Bnot,B);
not I3(Cnot,Cin);

and I4(S1,A,B);
and I5(S2,B,Cin);
and I6(S3,A,Cin);
and I7(S4,A,B,Cin);
and I8(S5,A,Bnot,Cnot);
and I9(S6,Anot,B,Cnot);
and I10(S7,Anot,Bnot,Cin);

or I11(Cout,S1,S2,S3);
or I12(Sum,S4,S5,S6,S7);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

一位元加法器行為模式

module top;
  integer A0,B0,Cin0;
  reg  A,B,Cin;
  wire Cout,Sum;
  mux_behavioral mux1(Cout,Sum,A,B,Cin);
  initial
    begin
      for (A0=0; A0<=1; A0 = A0+1)
        begin
          A = A0;
          for (B0=0; B0<=1; B0 = B0+1)
            begin
              B = B0;
               for (Cin0=0; Cin0<=1; Cin0 = Cin0+1)
                 begin
                   Cin = Cin0;
                 #1 $display("A=%d B=%d Cin=%d ",A,B,Cin,Cout,Sum);
                 end
             end
         end
    end
endmodule
module mux_behavioral(Cout,Sum,A,B,Cin);
 output Cout,Sum;
 input A,B,Cin;
 wire  A,B,Cin;
 reg   Cout,Sum;
always @(A or B or Cin)
 begin
   Cout = (Cin & (A^B)) | (A&B);
   Sum =  (Cin ^(A^B));
 end
endmodule

一位元加法器系統時脈設計與測試

module top;
wire a, b, cin;
system_clock #400 clock1(cin);
system_clock #200 clock2(a);
system_clock #100 clock3(b);

and a1(out1,a,b);
xor a1(out2,a,b);
and a2(out3,out2,cin);
xor a2(sum,out2,cin);
or c(cout,out1,out3);

endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

一位元加法器行為模式設計與測試

module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
               $display(" 0+1+1=10 sum is WRONG!");
              else
               $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out != 1 | sum !== 0)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(~a&~b&carry_in)|(a&b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

媽我又做到了!

階層是2位元多工器

module top;
  integer is;
  integer ia[1:0],ib[1:0];
  reg [1:0]a,b;
  reg s;
  wire [1:0]out;

   mux2 name2(out,a,b,s);

  initial
    begin
      for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)
        begin
          a[0]= ia[0];
          for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)
            begin
              a[1] = ia[1];
               for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)
                 begin
                   b[0] = ib[0];
                    for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)
                     begin
                      b[1] = ib[1];
                        for (is=0; is<=1; is = is + 1)
                       begin
                        s = is;
                 #1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d s=%d out[0]%d out[1]%d",a[0],a[1],b[0],b[1],s,out[0],out[1]);
                      end
                    end
                  end
              end
         end
    end
endmodule

module mux2(OUT,A,B,SEL);
 output [1:0]OUT;
 input [1:0] A,B;
 input SEL;

mux1 X1(OUT[0],A[0],B[0],SEL);
mux1 X2(OUT[1],A[1],B[1],SEL);

endmodule

module mux1(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;

 not n1(NOT_SEL, SEL);
 and a1 (X, A, NOT_SEL);
 and a2 (Y, SEL, B);
 or  o1 (OUT, X, Y);

endmodule

媽我成功了!