期末考試

module top;
wire a, b, c, d, f;
system_clock #400 clock1(a);
system_clock #200 clock2(b);
system_clock #100 clock3(c);
system_clock #50 clock4(d);

not a1(A,a);
not b1(B,b);
not c1(C,c);
not d1(D,d);
and f1(F1,a,C,D);
and f2(F2,a,b,C);
and f3(F3,a,b,d);
and f4(F4,b,C,d);
and f5(F5,A,B,c);
or out(F,F1,F2,F3,F4,F5);


endmodule`
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

期中

module top;
wire a, b, c, d, f;
system_clock #400 clock1(a);
system_clock #200 clock2(b);
system_clock #100 clock3(c);
system_clock #50 clock4(d);

not a1(A,a);
not b1(B,b);
not c1(C,c);
not d1(D,d);
and f1(F1,A,C,d);
and f2(F2,A,c,D);
and f3(F3,B,C,d);
and f4(F4,B,c,D);
or out(F,F1,F2,F3,F4);


endmodule`
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule