二位元加法器結構模式

module top;

wire [1:0] A, B, Sum;
wire Cout, Cin;

system_clock #400 clock(Cin);
system_clock #200 clock(A[1]);
system_clock #100 clock(B[0]);
system_clock #200 clock(B[1]);
system_clock #100 clock(A[0]);


adder2 M2(Cout, Sum, A, B, Cin);

endmodule

module adder2(Cout, Sum, A, B, Cin);
output [1:0] Sum;
output Cout;
input [1:0] A, B;
input Cin;

adder1 lo (C0,Sum[0],A[0],B[0],Cin);
adder1 hi (Cout,Sum[1],A[1],B[1],C0);

endmodule

module adder1(Cout, Sum, A, B, Cin);
output Cout, Sum;
input A, B, Cin;
not I1(Anot,A);
not I2(Bnot,B);
not I3(Cnot,Cin);

and I4(S1,A,B);
and I5(S2,B,Cin);
and I6(S3,A,Cin);
and I7(S4,A,B,Cin);
and I8(S5,A,Bnot,Cnot);
and I9(S6,Anot,B,Cnot);
and I10(S7,Anot,Bnot,Cin);

or I11(Cout,S1,S2,S3);
or I12(Sum,S4,S5,S6,S7);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule